1. Field
Exemplary embodiments of the present invention relate to an integrated circuit chip and a multi-chip system including the same, and more particularly, to a technique for facilitating a test of a multi-chip system.
2. Description of the Related Art
When a memory device, for example, Dynamic Random Access Memory (DRAM), Resistive Random Access Memory (RRAM), Phase-change Random Access Memory (PRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), and Flash memory, is completely fabricated, a test must be performed to check whether the memory device normally operates or not. In the test of the memory device, not only reliability of the test but also high speed of the test in several tens of millions of cells may be important. In particular, since development period of a memory device and test time of the memory device required until shipment have a direct effect on a fabrication cost, the reduction in test time emerges as an important issue in productivity and competition between makers. As a method for reducing a test time, a compression test (parallel test) may be used. The compression test is performed as follows. First, the same data are written to a plurality of cells, and then read through the use of an exclusive OR gate and the like. When the same data are read from the plurality of cells, a pass is determined and indicated as ‘1’, and when any one different data is read from the plurality of cells, a fail is determined and indicated as ‘0’.
In order to increase the integration degree of a memory, a three-dimensional (3D) structure including a plurality of memory chips stacked therein has started to be applied instead of an existing two-dimensional (2D) structure. As memories with a high integration degree and a high capacity are needed, a 3D stacked structure of a memory chip may be used to increase a capacity and reduce a semiconductor chip size, thereby improving the integration degree. As the 3D structure, a through-silicon via (TSV) structure may be applied. The TSV structure is considered as an alternative for overcoming the reduction of transmission speed depending on a distance from a controller on a module, the vulnerability of data bandwidth, and the reduction of transmission speed depending on variables on a package. The TSV structure includes a path formed through a plurality of memory chips and an electrode formed in the path, in order to perform communication between stacked chips.
When the compression test (parallel test) is performed in a 3D memory system including a plurality of memory chips stacked therein, it may be an important issue to use which method to facilitate the compression test.